New S2C Book on FPGA Prototyping: Download it for free immediately before they change their minds!

by Xilinx  ‎06-22-2016 03:26 PM

S2C has just published a 122-page book titled “PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design,” written by Semiwiki’s Dan Nenni and Don Dingee, and you’re going to want the free PDF download of this book even if you’re not currently using FPGA-based prototyping hardware. Why? Because there’s a ton of interesting FPGA history woven into this book.

Why did S2C publish this book? The book’s forward by S2C CTO Mon-Ren Chene explains:

“Nearly two decades ago during our time at Aptix, my S2C co-founder, Toshio Nakama and I recognized the power of prototyping. At that time, prototyping was only accessible by large design houses with the budget and means to employ a prototyping architecture. We also recognized that FPGAs had become a popular alternative to the much more expensive and rigid ASICs. It was then that we both decided to team up to develop a prototyping board around an FPGA, and S2C was born. Our commitment to our customers has been to push the limits of what FPGA prototyping can do to make designing easy, faster, and more efficient. Our goal has always been to close the gap between design and verification which meant that we needed to provide a complete prototyping platform to include not only the prototyping hardware but also the sophisticated software technology to deal with all aspects of FPGA prototyping.

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Fast forward to today and you’ll find that FPGAs and FPGA prototyping technology has advanced so much that designers and verification engineers can no longer ignore the value that they bring, especially when dealing with the very large and complex designs that we see today. These advances have made FPGA prototyping poised to become a dominant part of the design and verification flow. This book will hopefully give you a sense of how this is achieved.”

Here are some fun FPGA application facts from the book:

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“Strictly speaking, although it deployed Xilinx FPGAs and was essential in prototyping ASICs, the Quickturn RPM was the first commercial hardware emulator. From that point, advanced hardware emulator and FPGA-based prototyping platforms developed, on divergent paths for different use cases.”

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“Reconfigurable computing was the holy grail for signal processing, an ideal application for FPGAs with DSP-like primitives. An FPGA card could be added as a co-processor to an engineering workstation, and its logic architected to provide efficient data flow computational capability. The same workstation and FPGAs could be reconfigured for different applications quickly, especially if Xilinx SRAM-based FPGA technology were used.

Prime examples of early reconfigurable computing platforms were Splash 1 and Splash 2, originally created to perform DNA sequence comparison. Created in 1988, Splash 1 was a VMEbus system with 32 Xilinx XC3090 FPGAs in a linear systolic array. While powerful, the Splash 1 architecture quickly proved to be limited by the available FPGA interconnect, typically in the range of 200 to 300 pins and subject to clocking and delay variables.

Splash 2 began in 1991, upgrading to XC4010 FPGAs with a crossbar interconnect. It allowed chaining of up to 16 array boards each with 16 processing FPGAs (with a 17th part controlling the crossbar), and added an SBus adapter for easy connection to a Sun Microsystems SPARCstation.”

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 “Academic researchers took these concepts in a new direction, scaling down to run HDL chip designs of a few thousand gates in smaller FPGA-based rapid prototype boards. The idea behind rapid prototyping was software would run immediately with full fidelity to production silicon – or not. If the project did not have access or could not afford to fabricate a chip, a rapid prototype could still prove the validity of the concept.

The first of these rapid prototyping boards appearing in 1990 was the AnyBoard from North Carolina State University. It returned to a simple linear array of five Xilinx XC3090s and soon added automated circuit partitioning built on Xilinx place & route software. The partitioning software understood interconnect pins, clock rates, and logic and I/O constraints. Researchers compared gradient descent algorithms with a multi-bin version of Kernighan and Lin graph partitioning, testing designs of varying complexity.

Also in 1990, researchers at Stanford University created Protozone, a single Xilinx FPGA on a PC add-in card for experimentation. Protozone became a jumping-off point for other research projects in FPGA programming, but as a degenerate single-part configuration it did little to advance partitioning and routing science.”

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“The traditional knock on FPGA-based prototyping has been a lack of capacity and the hazards of partitioning, which introduces uncertainty and potential faults. With bigger FPGAs and synthesizable RTL versions of ARM core IP, many of the ARM core offerings now fit in a single FPGA without partitioning. Larger members of the ARM Cortex-A core family have been successfully partitioned across several large FPGAs without extensive effort and adverse timing effects, running at speeds significantly higher than simulation but without the cost of full-scale hardware emulation.

A hybrid solution has emerged in programmable SoCs, typified by the Xilinx Zynq family. The Zynq UltraScale+ MPSoC has a quad-core ARM Cortex-A53 with a dual-core ARM Cortex-R5 and an ARM Mali-400MP GPU, plus a large complement of programmable logic and a full suite of I/O. If that is a similar configuration to the payload of the SoC under design, it may be extremely useful to jumpstart efforts and add peripheral IP as needed.”

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Like I said, get the book.