CAST Releases H.264 IP Core for Highest Quality HD Video Compression
Woodcliff Lake, NJ, July 15, 2009 — Silicon Intellectual Property (IP) provider CAST, Inc. today announced the immediate availability of a new H.264 encoder core that delivers some of the best looking compressed video available.
The CAST H264-E Encoder is intended for applications that require the transmission of the highest quality video over low bit-rate channels, including remote medical diagnostics, military targeting, satellite reconnaissance, and advanced surveillance systems. It offers this quality for screen sizes from handheld (CIF, 352 x 240 pixels) to full HD (1080p30, 1920 x 1080 at 30 frames per second).
The core fully supports the Baseline Profile, Level 4.1, of the H.264 specification (MPEG-4 Part 10, also known as MPEG-4 AVC, Advanced Video Coding). That specification, however, defines a format, not a means for achieving it, and the quality of output can vary across implementations. Every design decision in the CAST H264-E development process was made in favor of improving video quality. This uncompromising approach led to excellent output and nearly constant-quality video for even the most demanding compression challenges: high-motion scenes, quick camera panning, rapid scene changes, artificial motion, and frequent zooming.
Achieving this video quality with just Baseline Profile support means the CAST H264-E generally requires fewer resources—processing time, chip area, and power consumption—than competing cores that support higher-level profiles. In fact, the H264-E readily fits and performs well in popular FPGA devices as well as ASICs, including Altera Corporation's low cost Cyclone® III devices and the rest of the company's FPGA and HardCopy ASIC families, and the Xilinx® high-performance Virtex®-4 and Virtex®-5 device families.
"Altera and CAST have been partners for many years providing video codec cores for Altera customers," said James Smith, director of product marketing, IP partnerships at Altera Corporation. "CAST offers impressive video image processing, and its new H.264 encoder core will complement Altera's own extensive video processing IP."
"As Xilinx continues to expand its range of technology specific products and platforms targeting market specific customers, our ecosystem plays a key role in the whole product offering. CAST, a Xilinx Alliance member, offers top quality IP for Image Processing and is an integral part of the ecosystem assuring customer successes," said Mark Jensen, Director of Industrial, Scientific, and Medical Segment Marketing at Xilinx.
The core is available now, in RTL source code for ASICs or optimized netlists for programmable devices. A full description of its features, technical details, end examples of objective quality measures are available. Moreover, The H.264 encoder IP core, together with several other CAST IP cores, are implemented in a Xilinx Virtex-5 FPGA on S2C's TAI Logic Module. The reference design reads a video file in standard YUV format and accepts various compression parameters set through a GUI on the host system. It then produces H.264 video, which is sent through the PCIe connection for streaming display or file storage. The reference design will greatly reduce IP evaluation time and ease design prototyping for SoC designers. Interested customers can see the demo at DAC (CAST's booth 1421), or contact S2Csales@s2cinc.comto request the demo locally in China.
Founded and headquartered in San Jose, California, S2C is the leading total solution provider in facilitating systems to chip innovations. S2C has four solutions for system-on-chip (SoC) development:
- Rapid SoC prototyping on Field Programmable Gate Array (FPGA)
- Third-party silicon intellectual properties (IP)
- Customizable, zero mask-charge eASIC semiconductor devices
- SoC design, prototype and production Servicess
S2C's value proposition is our highly qualified engineering team and customer-focused sales force that understands our customers' commercial needs in SoC development. S2C's unique FPGA-based electronic system level (ESL) solution, using our patented TAI IP technology, enables designers employ silicon IP to quickly assemble SoC prototypes on FPGA easily and securely, thereby enabling customers to start software development, typically the long pole item in development schedules, immediately. Combining rapid prototyping methodologies with a comprehensive portfolio of silicon IP and advanced design solutions, S2C can reduce the SoC design cycle by up to nine months.
S2C currently has 3 direct offices located in Shanghai, Beijing and Shenzhen to meet the demand for accelerated SoC design activities in China. S2C is also the organizer of the annual SoCIP seminar and exhibition in China, which brings SoC designers/professionals from the Asia-Pacific region together with international silicon IP and SoC solution vendors.
For more information, please contact: Lawrence Liang, Sales Director of China Region, S2C Inc. +86 21 6887 9287, email@example.com Lam Cheng En, Marketing Consultant, S2C Inc., +86 21 6887 9287, firstname.lastname@example.org