S2C Debuts eASIC Solutions for Solving ASSP business Challenges at SoCIP Event in China
Shanghai, China – September 25, 2008—S2C, a solution provider for accelerating System-On-Chip (SoC) Innovations, today announced an agreement to distribute eASIC NEW ASIC products in China. eASIC’s zero mask-charge, no minimum order quantity NEW ASICs address Application Specific Standard Product (ASSP) business challenges such as skyrocketing chip design costs and shrinking product life cycles. Electronics System Designers are invited to attend the first annual SoCIP event in Beijing on October 13th and in Shanghai on October 15th to learn more about reducing the cost of ASSP and ASIC design.
eASIC, a fabless semiconductor company headquartered in Santa Clara, California, offers breakthrough low-cost, high-performance and fast-turn semiconductor devices through its patented single via-layer customizable routing technology. eASIC’s 90nm Nextreme NEW ASIC product was introduced in October 2006 and had more than 120 design-wins within the first 18 months. The latest Nextreme-2 NEW ASIC family is the industry’s first 45nm, zero mask-charge and customizable semiconductor device family that enables SoC designers to integrate up to 20 million logic gates, 30 million bits of memory and 56 6.5Gbps transceivers in a single device. eASIC’s NEW ASIC devices feature a simple design flow using optimized, low-cost Magma tools, and the ability to deliver working devices in four to six weeks.
“Electronics OEMS and ODMs in China need to innovate quickly but continue to drive design costs lower but designing the right ASSP product for fast pace electronic market is increasingly becoming difficult especially when ASSP design costs are skyrocketing. Traditional Standard Cell ASICs are becoming more and more expensive to design as process nodes get lower and this has resulted in dramatic decline in the number of standard cell ASIC-based design starts,” said Jasbinder Bhoot Senior Marketing Director, eASIC Corporation.. “eASIC’s NEW ASIC products enable SoC design companies to overcome their current ASSP business challenges through facilitating shorter development time and a fraction of up-front cost compare to conventional standard cell-based design. As a result, SoC design companies will have much higher rate of meeting the product specifications required by today’s dynamic end consumers and thereby creating profits from the development projects.”
“Through business engagements with many SoC/ASSP design companies in the Far East in the past 5 years, we can clearly see the disproportion between the amount of effort a chip design company needs to invest and the amount of return after factoring in all the risks,” said Toshio Nakama, Chief Executive Officer of S2C. “The biggest risk of all is will the SoC product still meets the market demands after up to 24 months of design cycle and expensive up-front design and manufacturing expense. Most ASSP companies that fail are not because they can’t build the SoC right, but they can’t build the right SoC for the market. We truly believe that it’s time that the ASSP companies take the step to adopt eASIC low-cost, high-performance and fast-turn solution to overcome the business challenges especially when designing using 90nm and more advanced process technologies. ”
More details of how eASIC products can address the ASSP business challenge will be presented at the SoCIP 2008 events at Beijing on October 13th and Shanghai on October 15th. SoCIP is an annual seminar and exhibition dedicated to the SoC design industry in China, bringing together the regional SoC designers/professionals and the international silicon IP and SoC solution vendors. For more information about the SoCIP 2008 event, please visit http://www.s2cinc.com.cn/SoCIP2008/.
eASIC is a fabless semiconductor company offering breakthrough zero mask-charge, no minimum order quantity New ASIC devices dramatically reducing overall cost and production times for customized semiconductor devices. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology utilizing Via-layer customizable routing. Privately held eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, Advanced Equities Incorporated and Evergreen Partners. For more information, please visit www.eASIC.com
Founded and headquartered in San Jose, California, S2C has been successfully delivering rapid SoC prototyping solutions since 2003. S2C provides:
- Rapid SoC FPGA-based prototyping hardware and automation software
- Prototype Ready™ IP, Platforms, and Accessories
- System-level design verification and acceleration
S2C's value is our singular focus on SoC/ASIC development. Our highly qualified engineering team and customer-focused sales force understands our customers’ SoC development needs. S2C’s unique FPGA-based solution, using our patented TAI IP technology, enables designers to quickly assemble FPGA-based SoC prototypes on S2C FPGA boards. This gives customers an early start on software development, typically the long pole item in development schedules. Combining rapid prototyping methodologies with a comprehensive portfolio of Prototype Ready IP and advanced verification and acceleration solutions, S2C solutions greatly reduces the SoC design cycle.
In addition to the headquarters in San Jose, CA, S2C currently has 4 direct offices located in Shanghai, Beijing, Shenzhen China and HsinChu, Taiwan. S2C is also the organizer of the annual SoCIP seminar and exhibition in China, which brings SoC designers from the Asia-Pacific region together with international silicon IP and SoC solution vendors. For more information, visit www.s2cinc.com.
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S2C, Prototype Ready and TAI, are trademarks of S2C, Inc. All other tradenames and trademarks are the property of their respective owners.