Hardware Verification

Challenges

We all know that complexities in design and shrinking time-to-market windows are driving up design and verification costs. Simulation and emulation, although useful, are slow and for the later also costly. Furthermore, both simulation and emulation can hit a wall when it comes to identifying critical corner case bugs. A hardware platform such a FPGA prototyping is more cost-effective and much faster with the ability to test system designs at speed to provide an accurate assessment of design behavior. However, compiling complex designs to multiple FPGAs can still be time-consuming and debugging designs with multiple FPGAs can be difficult.

Innovative Technology

The cost and speed benefits of FPGA prototyping can be reaped through the use of S2C’s Prodigy Prototyping technology. S2C’s advanced partitioning software utilizes an LVDS pin-multiplexing scheme to quickly map designs to FPGA(s).

Debugging is a critical component of verification of large designs and again, advances in debug technology for FPGA prototyping has helped to alleviate concerns about debugging multi-FPGA partitioned designs. S2C’s Prodigy debug technology allows for visibility of multiple FPGAs at the same time eliminating crucial debug errors and dramatically reducing debug time. By using external memory, S2C’s solutions can also increase debug capacity to achieve deep design debug and find critical hard to find bugs.

S2C Prodigy Prototyping Solutions

Thorough and complete hardware verification can be achieved using the following Prodigy Prototyping hardware and software solutions:

Hardware

Software