| Title : |
RTL Design Engineer |
| Job Location : |
Shanghai, China |
| Job Responsibilities : |
1. Work with S2C's core tools.
2. Develop IP blocks in RTL and test/validate them on FPGA boards.
3. Responsible for writing specifications and helping the project leader complete complex designs. |
| Job Requirements : |
1. Minimum BS in CS/EE with 3+ years experience, or MS in CS/EE with 1+ years of experience, in ASIC/FPGA front-end design.
2. Knowledge of logic design flow and experience in Verilog RTL & testbench coding.
3. Understanding of VHDL is a plus.
4. Familiarity with simulation/synthesis/FPGA P&R tools.
5. SoC design know-how is preferred.
6. Excellent interpersonal skills.
7. Strong motivation to learn new skills and explore different technologies. |
| Post Date : |
October 30, 2006 |
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