FPGA-Based SoC Design
- Design Flow
- TAI IP
- TAI Architecture
- Solution Benefits
FPGA-Based SoC Design
Our rapid FPGA-based SoC design methodology is a system-level design flow in which designers use plug-and-play FPGA-based IP modules to create system configurations that are both accurate and high-performance. FPGA-Based SoC Design
As the figure below illustrates, designers can perform architectural design, IP integration, software development, HW/SW co-verification, and FPGA prototyping all in the same FPGA-Based SoC Design design platform.
For all these benefits, however, conventional FPGA-based IP modules are not readily compatible with each other and are difficult to debug. With S2C's TAI IP technology, system designers can now enjoy the benefits of FPGA-Based SoC Design design without having to deal with its conventional drawbacks.
- Verify the system and software before RTL development
- Design and verify the system on a single FPGA-based platform
- Correlate actual design implementation with system level models
TAI IP technology makes FPGA-Based SoC Design design possible by facilitating FPGA-based IP compatibility and analyzability.
TAI IP is an encrypted representation of any IP in FPGA netlist format with TAI structure insertions that make the IO of the IP in FPGA dynamically configurable, even in FPGA binary format. As a result, when multiple TAI IP blocks communicate with each other, they can be intelligently linked through dynamic communication channels without having to be recompiled due to configuration changes.
“TAI” signifies the enhanced functionalities of Testability, Analyzability, and Integratability that TAI IP possesses over conventional IP formats.
Intelligently links non-uniform test structures from IP with different test standards, allowing both system-level and chip-level testing as well as fault simulation, thereby empowering designers to more quickly isolate problems.
Enables analysis of IP data from a high level of abstract, without the user having to understand IP details and/or access the IP source code – resulting in earlier development of both software and firmware.
Simplifies integration of disparate IP into SoCs and combines disparate IP into multiple FPGAs. Ubiquitous bus interface technology seamlessly configures different bus standards into the targeted bus architecture.
TAI IP Benefits
- Easy to create – Compiled from actual RTL netlist
- Clock Accurate – Functional
- Fast – Run at or near target speeds
- Analyzable – Embeds symbols and events
- Integratable – Plug-and-playable
- Secure – Thwart reverse engineering
Our FPGA-Based SoC Design design solution provides a truly scalable FPGA prototyping architecture for TAI IP to plug-and-play into FPGA prototypes and intelligently debug designs in FPGA.
S2C and S2C's hardware partners provide a variety of FPGA prototypes that follow the TAI-compliant architecture, which is open to licensing by customers and hardware partners who want to build TAI-Compliant FPGA prototypes.
For more information, please contact S2C sales: firstname.lastname@example.org.
- Infuses FPGA prototypes with attributes of scalability, plug-and-playability, and full interconnectability.
- Facilitates powerful system level debugging for SoC designs mapped to a large number of FPGAs.
- Allows secure IP evaluation and integration in the form of an FPGA-based model.
- Supports automatic software compile flow that infuses FPGA-mapped IPs with integratable and analyzable attributes.
- Reuses prototyping hardware efficiently.
All FPGA prototypes and products that comply with TAI architecture are affixed with the TAI-Compliant logo as shown below. Third-party hardware vendors can use the TAI-Compliant logo on their FPGA prototypes as well as related literature and packaging once S2C certifies the prototypes as TAI-compliant.
Linking FPGA-based and Software-based ESL through SCE-MI Co-Modeling Interface
TAI IP-enhanced FPGA-Based SoC Design can be used not only independently but also combined with software-based ESL to enable early architectural exploration and algorithm development.
For instance, a designer may sometimes rely on SystemC models for a preliminary design at the beginning of the design process. In this case, the designer can place the SystemC models in PC-based tools and the remainder of the design in the FPGA-Based SoC Design platform. The various parts of the model can then communicate at the transaction level through the Accellera standard SCE-MI interface with the use of synthesizable transactors (aka bus functional models (BFM)).
S2C's SCE-MI allows users to link designs in FPGA to C, C++ and SystemC. Furthermore, with the usage of higher-level C-API, designers can also link designs in FPGA with Instruction Set Simulators (ISS) such as Armulator as illustrated in the diagram below.
Linking FPGA-Based SoC Design to high-level design models in PC allows users to realize complete system architectural validation without having all the IP blocks in FPGA. Because data are transferred at the transaction-level between PC and FPGA hardware, most designs can run at speeds in the MHz range.
Another instance where linking FPGA- and software-based ESL would be beneficial is when prototyping speeds do not match the real targets. In Gigabit Ethernet applications, for example, an FPGA prototype may have a hard time running at the same speeds as those of the target, so the designer can work around this limitation by using high-level modeling of the target in a PC and exercising the design in FPGA through SCE-MI interface.
S2C SCE-MI Interface Solution
< Example >
Accelerate SoC Product Time-to-Market by 3~6 Months
FPGA-Based SoC Design design flow brings you straight from design specification to FPGA prototype by creating system configurations using TAI IP. This approach eliminates the ESL to RTL correlation problems often encumbering other system design methodologies. You don't have to worry about translating behavioral ESL models to RTL or converting existing RTL models to behavioral models for system level design. In addition, software can be developed on fast, accurate FPGA prototypes from the beginning of the design process.