Scroll down the page to view the S2C methodology glossary, or jump to specific terms by using the letter index.
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Glossary of Terms |
ASIC
Application-Specific Integrated Circuit. An integrated circuit with preset logic designed to perform a specific function.
ASIC Emulator
A hardware system that emulates the design of an ASIC before it is built. ASIC emulation is the traditional method designers use to check the function and integrity of a design, as it can run at speeds many times faster than software simulation. With the advance of FPGA technology, many designs are now emulated on FPGA prototypes, which are less costly and provide higher performance.
ASIC Prototyping
Commonly refers to the prototyping of ASIC on FPGA for logic verification prior to silicon fabrication.
BFM
Bus Functional Model. A functional, accurate model of a bus that enables high abstraction level simulation models or languages to co-simulate with bus interfaces at much higher throughput levels than traditional simulations can achieve.
Co-Modeling
A method of verification that links software simulation models to hardware models, usually in FPGA-based form. Co-modeling often specifically refers to the linking of hardware models to higher abstraction level software simulation models through a transaction-based interface.
Co-Simulation / Co-Emulation
A method of verification that links RTL-level simulation to FPGA-based prototypes or ASIC emulators.
DUT
Design Under Test. Refers to the system or unit that is undergoing testing or simulation.
EDA
Electronic Design Automation. Software tools used for the development of integrated circuits and related systems.
EDIF
Electronic Design Interchange Format. A netlist format that can be used to transfer information from synthesis to place-and-route tools.
ESL
Electronic System Level. An integrated circuit design methodology that models at a high level of abstraction, focusing on overall system functionality and allowing for concurrent hardware and software design.
FPGA
Field Programmable Gate Array. A silicon chip whose logic can be programmed after manufacturing.
FPGA-Based ESL
An ESL environment using FPGA-based IP models.
FPGA-Based Prototype
A prototype of an SoC or ASIC using FPGAs.
FPGA Prototyping
The prototyping of ASIC on FPGA for logic verification prior to silicon fabrication.
Hard IP
A fixed form of intellectual property that is formatted in a physical design layout.
ILA
Internal Logic Analyzer. A hardware-embedded electronic instrument that translates the signals of a digital circuit in visual form – typically used for real-time FPGA debugging.
Intellectual Property (IP)
Intellectual Property. In EDA, typically refers to silicon IP.
RTL
Register Transfer Level. A high-level hardware description language that describes the registers of an electronic system at a low level of abstraction. VHDL and Verilog are examples of RTL languages.
SCE-MI
Standard Co-Emulation Modeling Interface. An application programming interface standard that enables communication between designs in software simulations and in hardware models at transaction-level abstractions.
Simulation Acceleration / Accelerator
The use of high-level languages or hardware-assisted methods to accelerate software simulation speed.
Simulation Model
A software-based model designed to replicate the timing and behavior of an IC design for the purposes of verification and debugging.
Software / Hardware Co-Design
The concurrent development of both software and hardware aspects of the SoC IC design process through use of high-level abstraction simulation or FPGA-based prototypes and/or ASIC emulators.
Silicon IP
Silicon Intellectual Property. Reusable design blocks that can be utilized for building different SoCs.
SoC
System-on-Chip. A single IC that functions as a whole system or sub-system, which combines at least one processor, digital IP, analog IP, memory, firmware , and software.
SoC Prototyping
The methodology of creating a working model of an SoC's various components (hardware, software, and firmware) through an FPGA-based prototype for the purpose of system validation, hardware verification, and early software and firmware development.
Soft IP
A synthesizable RTL form of silicon IP that can be used for both silicon manufacturing and FPGA prototyping.
TAI IP
S2C's proprietary silicon IP format that is used for secure IP evaluation and integration on FPGA-based prototype. TAI IP is an encrypted representation of any IP in FPGA netlist format with TAI structure insertions.
TAI Logic Module
S2C's FPGA-based prototyping hardware that can be used for ASIC and SoC prototyping.
Transaction-Based Verification
A technique that verifies bus protocols, such as PCI, through test bench at the transaction level of abstraction. Transaction-based verification is becoming a popular methodology for verifying complex SoCs that have multiple bus standard interfaces for the transfer of data between RTL blocks and the ESL portion of an IC's design – allowing emulation to begin at an earli er stage.
Vector-Mode Testing
A method of design testing using a large number of test vectors. Vector-mode testing can also be used for testing designs in FPGA prototype by using test vectors stored in hard disk through a PC-to-prototype interface.
Verification IP
Verification Intellectual Property. A type of reusable IP that can generate comprehensive tests for shortening SoC verification and increasing test coverage. Verification IP is often used to verify standard bus protocols.
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