Linking FPGA-based and Software-based ESL through SCE-MI Co-Modeling Interface
TAI IP-enhanced FPGA-based ESL can be used not only independently but also combined with software-based ESL to enable early architectural exploration and algorithm development.
For instance, a designer may sometimes rely on SystemC models for a preliminary design at the beginning of the design process. In this case, the designer can place the SystemC models in PC-based tools and the remainder of the design in the FPGA-based ESL platform.  The various parts of the model can then communicate at the transaction level through the Accellera standard SCE-MI interface with the use of synthesizable transactors (aka bus functional models (BFM)).
S2C's SCE-MI allows users to link designs in FPGA to C, C++ and SystemC. Furthermore, with the usage of higher-level C-API, designers can also link designs in FPGA with Instruction Set Simulators (ISS) such as Armulator as illustrated in the diagram below.
Linking FPGA-based ESL to high-level design models in PC allows users to realize complete system architectural validation without having all the IP blocks in FPGA. Because data are transferred at the transaction-level between PC and FPGA hardware, most designs can run at speeds in the MHz range.
Another instance where linking FPGA- and software-based ESL would be beneficial is when prototyping speeds do not match the real targets. In Gigabit Ethernet applications, for example, an FPGA prototype may have a hard time running at the same speeds as those of the target, so the designer can work around this limitation by using high-level modeling of the target in a PC and exercising the design in FPGA through SCE-MI interface.
S2C SCE-MI Interface Solution
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