Secure IP Evaluation
S2C's TAI IP format and FPGA-based ESL tools are the ideal vehicles for secure IP evaluation and delivery. Our secure IP evaluation solution enables users to evaluate IP on FPGA prototypes before purchasing – and without requiring access to the IP source code. IP security continues to be the major obstacle to IP licensing in many developing markets worldwide.
S2C's IP evaluation solution first maps IP in source code format to TAI IP format using TAI Compiler® for secure quick prototyping. The IP can then be evaluated on TAI-compliant FPGA prototypes using RTL simulators, ESL simulators, test vectors, or real target environments.
Since the TAI IP compile process can be performed by either the IP provider or S2C, the IP evaluator may not have access to the IP source code. Furthermore, symbols and high-level transactions can be embedded in the TAI IP during the compile process; as such, IP evaluators can easily analyze the IP on FPGA prototype from a system level perspective even without access to the source code.
The diagram illustrates S2C's secure IP evaluation flow and compares it to two conventional IP evaluation methods.
S2C Secure IP Evaluation Flow |
Conventional IP Evaluation Flow
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A secure IP evaluation platform can be conveniently set up using S2C's FPGA-based ESL tools. The diagram below illustrates a sample evaluation platform of Tensilica's 108 mini core.
Tensilica 108 Mini Evaluation Kit
Click on the box below to check available IP that can be evaluated out-of-box. If you would like to request an IP that is not on the list, please contact S2C at info@s2cinc.com.
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