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TAI IP

TAI IP – The Breakthrough in FPGA-based ESL Design
TAI IP technology makes FPGA-based ESL design possible by facilitating FPGA-based IP compatibility and analyzability. TAI IP is an encrypted representation of any IP in FPGA netlist format with TAI structure insertions that make the IO of the IP in FPGA dynamically configurable, even in FPGA binary format. As a result, when multiple TAI IP blocks communicate with each other, they can be intelligently linked through dynamic communication channels without having to be recompiled due to configuration changes.

“TAI” signifies the enhanced functionalities of Testability, Analyzability, and Integratability that TAI IP possesses over conventional IP formats.

>> Testable
Intelligently links non-uniform test structures from IP with different test standards, allowing both system-level and chip-level testing as well as fault simulation, thereby empowering designers to more quickly isolate problems.

>> Analyzable
Enables analysis of IP data from a high level of abstract, without the user having to understand IP details and/or access the IP source code – resulting in earlier development of both software and firmware.

>> Integratable
Simplifies integration of disparate IP into SoCs and combines disparate IP into multiple FPGAs. Ubiquitous bus interface technology seamlessly configures different bus standards into the targeted bus architecture.

TAI IP Benefits

	Easy to create – Compiled from actual RTL netlist
	Clock Accurate – Functional
	Fast – Run at or near target speeds
	Analyzable – Embeds symbols and events
	Integratable – Plug-and-playable
	Secure – Thwart reverse engineering