8051-Based Platforms

R8051XC-CUSB2 Embedded USB Subsystem

The R8051XC-CUSB2 subsystem combines an 8-bit processor core, a USB 2.0 full- or hi-speed device controller core, and a USB software stack to provide USB connectivity for System on Chip (SoC) designs.

• The 8051 embedded USB subsystem reference design platform include:
  • R8051XC Fast, Configurable Microcontroller Core
  • CUSB2 (or CUSB) USB Device Controller Core

Block Diagram

Sample Application

This subsystem sample application works as a USB Mass Storage system. It transmits data between the hard disk drive and the PC using the subsystem's USB connection. The CPU controls the settings of endpoints and Services interrupts. The main data transfer is performed by the 8051 CPU and DMA to and from the hard disk by means of an ATAIF controller.

R8051XC-MAC-L Embedded Internet Subsystem

The R8051XC-MAC-L subsystem combines an 8-bit processor core, a 10/100 Mbps Ethernet MAC device controller core, a hardware accelerator, and a TCP/IP software stack to provide Internet connectivity for system-on -chip (SoC) designs.

The subsystem's pre-integrated cores work together as a fast, compact, programmable Ethernet controller. The R8051XC Microcontroller Core executes the MCS®51 instruction set with just one clock per cycle, has numerous optional features and peripherals capabilities, and has been proven in hundreds of customer designs. The MAC-L Media Access Controller Core supports full- and half-duplex operation, has a Media Independent Interface (MII) for simple control, and includes a parameterized, multi-packet FIFO implemented using dual-port RAMs.

A custom Hardware Accelerator core also integrated in the subsystem efficiently controls checksums for common TCP/IP protocols like TCP, IPv4, UDP, and ICMP.

The subsystem also includes the proven TCP/IP software stack from. This features a MAC-L driver for optimum operation with the 8051 and Ethernet cores.

The subsystem is designed for reuse in ASIC, eASIC, and FPGA implementations. The design is strictly synchronous with positive-edge clocking and a synchronous reset without internal tri-states; therefore, the scan insertion is straightforward.