TAI Player Pro - Compile
The TAI Player Pro Compile Module dramatically eases your SoC prototyping labor particularly for designs that requires partitioning across multiple FPGAs. With a straightforward graphical user interface, you can perform prototype testing in a fraction of the time it would have taken following the conventional design flow. TAI Player Pro is a front-end to Altera, Xilinx and other third party synthesis, place and route and debug tools. The user can stay in a common environment while moving between Altera and Xilinx flows. RTL-level probes are set up before synthesis so names can be retained through out the compile flow even when design are partitioned across multiple FPGA.
1. Set Up Probes in RTL Level
Easily locate any wire or register in RTL level design tree. TAI Player software automatically pulls these probes to either the FPGA boundary or to the ILA.
2. EDIF Level Partition
Choose which of your design modules to be grouped together and TAI Player automatically partitions the rest of your design modules onto multiple FPGA.
3. Assign I/O
Simply assign daughter board connectors to FPGA board connectors for I/O pin assignments. TAI Player provides a library of S2C daughter board pin-map files and the user can add in their own daughter board pin-map files.