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IP Porter – FPGA-based ESL Design Platform
IP Porter is the world's first FPGA-based ESL design platform facilitating system design using TAI IP – an FPGA-based ESL methodology. The IP Porter system includes TAI-compliant FPGA prototyping hardware and S2C Navigator software that configures system design using TAI IP. IP Porter links to SystemC and other standard ESL tools through SCE-MI and C-API.
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Benefits
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Scalable large capacity system |
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-- Single system holds 3M user ASIC gates
-- 20Mbits FPGA internal memory and up to 1GB of built-in SDRAM |
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Small form factor and high performance |
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USB2.0 interface for design downloading and debugging |
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Intuitive and integrated software flow |
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-- Compile Verilog and VHDL |
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-- Embedded automatic partition engine |
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Powerful debugging capabilities |
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-- Integrated Logic Analyzer |
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-- Link with standard RTL Simulators |
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-- Vector Mode testing |
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-- Embedded symbols in TAI IP enable system level debugging without detailed knowledge of IP |
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Cost-effective replicates for software development |
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