FPGA-based Prototyping Development Kit：TAI PDK
The Dual Virtex-4 TAI Prototyping Development Kit (TAI PDK) is an integrated FPGA-based prototype design suite that enables IC designers to easily construct efficient SoC prototypes in a cost-effective manner. The design kit is comprised of three flagship S2C products – Dual Virtex-4 TAI Logic Module prototyping board, TAI Pod prototype-to-PC hardware interface, and TAI Player design flow automation software.
TAI PDK comes in two logic capacity levels: the TAI-PDK-4V200D offering 4 million logic capacity gates (two Xilinx Virtex-4 LX200 FPGAs) and the TAI-PDK-4V160D offering 3.2 million logic capacity gates (two Xilinx Virtex-4 LX160 FPGAs).
Capacity
- up to 4 million ASIC gates with two Xilinx Virtex-4 LX200 FPGAs
- up to 3.2 million ASIC gates with two Xilinx Virtex-4 LX160 FPGAs
Performance: 500 MHz clocking in single FPGA, 400 MHz differential FPGA to FPGA
32 global clocks
480 dedicated external IOs
624 inter-FPGA connections, can be used as external IO
Compile Verilog / VHDL
Support bottom-up and incremental synthesis using XST and Synplify/Synplify Pro
Group IP (design modules) into different FPGA automatically or through instance groups,
flattening hierarchy features to guide FPGA grouping
Automatically handle internally generated clocks and asynchronous reset
Assign IOs and their properties in GUI, avoiding errors
Fast and easy FPGA download from PC
Advanced clock generation
- 4 configurable base clocks from 1 MHz to 200 MHz
- 16 phase-adjustable synchronized clocks generated from 4 base clocks
