USB 2.0 High Speed Device Controller Core
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The USBHS-DEV core implements a complete high/full-speed (480/12 Mbps) peripheral controller that interfaces to a UTMI USB port transceiver on one side and to a system’s microprocessor on the other. It is user-configurable for up to 15 IN and OUT endpoints, and includes power management and remote wake-up functions. Options include a protocol aware DMA controller, support for a variety of widely used bus interfaces, and a UTMI Low Pin Interface (ULPI). Designed for easy reuse in ASIC and FPGA implementations, the microcode-free design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward.
Features
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- Full compliance with the USB 2.0 specification
- Control endpoint 0: fixed 64 Bytes size
- Configurable for up to 15 IN and 15 OUT endpoints
- Configurable/programmable number and size of endpoints
- Configurable/programmable single, double, triple or quad buffering
- Programmable type of endpoints
- UTMI Transceiver Macrocell Interface. Optional UTMI Low Pin Interface (ULPI).
- Choice of different microprocessor interfaces:
- AMBA AHB
- PVCI
- Generic
- Configurable 8-, 16-, or 32-bit microprocessor interface
- Easy integration with a wide range microprocessors and bus architectures
- Interrupt request signals for application microprocessor
- Interrupt vector for autovectored interrupts
- Direct access to the endpoints buffers via configurable 8-, 16-, or 32-bit Data Interface
- Ready for external DMA module
- Synchronous RAM interface for FIFOs
- Optional protocol-aware DMA controller with configurable number of channels
- Suspend and resume power management functions
- Remote Wake-Up function
- Optional software stack
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
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Block Diagram
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