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I2S Multi-Channel Core

The I2S-MC core integrates eight channels of Inter-IC Sound compatible serial buses. I2S is a well-known stereo audio transmission standard, widely used to connect system elements such as Analog to Digital and Digital to Analog converters.

By using the I2S-MC module in a SoC design, a designer can easily integrate the core used for multi-channel audio transmission with the master system based on a standard AMBA APB bus for further data processing. In order to facilitate the use of the I2S core in AMBA bus based microprocessor systems, it is provided with an AMBA? APB bus wrapper, transmit and receive FIFO control units, special function registers block (SFR), and 8-channels of the I2S core.

Features

Meets Philips Inter-IC Sound Bus Specification
Supported modes
I2S Philips
Left Justified
Right Justified
DSP
Two clock domains
APB the host side clock do-main
system clock for the I2S channels
Eight configurable stereo chan-nels
Two sets of SCK (SCLK) and WS (LRCLK) strobes
one for all transmitters
one for all receivers
AMBA APB bus slave interface for data and configuration
Contains two configurable FIFO buffers
one for all transmit channels
one for all receive channels
One configuration register block for all channels
Interrupts driven by the I2S bus activity events
Handshake interface to external DMA modules
Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)

I2S Multi-Channel Core

Features

Block Diagram