The LJPEG-D decodes images that conform to the spatial (sequential) lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T.81 recommendation). Rather than the Discrete Cosine Transform (DCT) functions used for lossy JPEG compression - which can introduce round-off errors - the lossless part of the standard employs a reversible predictor function. The LJPEG-D core can thus decode images with no information loss, and requires a smaller physical implementation than what necessary for lossy JPEG image decoding. Evaluation designs show that the core requires just 36K gates in an ASIC and that it fits in a variety of low-cost FPGA devices. Its heavily optimized architecture also enables very high performance, reaching 500 MSamples/sec on 90nm process (under typical process and operating conditions). The LJPEG-D is a fully synchronous, strictly positive-edge design with no internal three-state buffers. Comprehensive documentation and a complete verification environment - including a bit-accurate model - help designers integrate and verify the core.
- Conforms to the spatial (sequential) lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T81 recommendation).
- Standalone operation.
- ISO/IEC 10918-1 JPEG stream input.
- Decoded pixel samples output.
- Self-programmable through the standard JPEG markers.
- Programmable image dimensions.
- Full range sample precision support (2 to 16 bits per sample)
- Up to four stream-programmable Huffman tables.
- Programmable Restart Interval.
- Programmable Point Transform function.
- Header errors catch-up features.
- Compact, high-performance architecture.
- 36K gates achieving 500 MSamples/sec (90nm ASIC ) under typical process and operating conditions.
- Also fits low-end FPGA devices (see FPGA version datasheets).
- Robust and simple to use
--General purpose, fully stallable, streaming I/O interfaces.