SHA1 Secure Hash Algorithm Core
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The core is composed of two main modules, the SHA1 Engine Module and the Input Interface Module as shown in the block diagram. The SHA1 Engine Module applies the SHA1 loops on a single 512-bit message block, while the Input Interface Module performs the message padding. The processing of one 512-bit block is performed in 82 clock cycles, and the bit-rate achieved is 6.24Mbps/MHz on the input of the SHA1core. The SHA1 core is equipped with fully-stallable input and output interfaces. These enable the user’s application to stop the input stream according to a data arrival rate, or to stop the output stream when the core is not able to receive data. The core has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs. Representative results show it to produce a competitive implementation, running at 350MHz and requiring just 14,500 gates in a .18um ASIC process. The complete deliverables feature comprehensive documentation, and a bit-accurate software model (BAM).
Features
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- Compliant to the FIPS 180-1 specification for SHA-1.
- 2**64-1 bits maximum message lenght.
- Bit padding.
- Supported Message lengths multiple of 8-bits
- Initial values of Chaining Variables selected before synthesis
- 82 processing cycles per message block
- Fully stallable input and output interfaces, ideal for streaming applications.
- Optimized design for ASIC or FPGA implementations.
- Robust verification environment includes bit-accurate software model.
- Scan-ready design architecture
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Block Diagram
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