C68000-AHB 32-bit Microprocessor
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The core uses an AMBA-compatible AHB master interface, making it an ideal processor solution for low-cost, AHB-based System on Chip (SoC) applications. The C68000-AHB is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous without internal tri-states and with a synchronous reset. Scan insertion is straightforward. Native On-Chip Debugging Support (OCDS) is available as an option to facilitate embedded processor debugging.
Features
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- Control Unit
- 16-bit two levels instruction decoder
- Three levels instruction queue
- 55 instructions and 14 address modes
- Supervisor and User mode:Independent stack pointer for both modes
- Users registers
- Eight 32-bit data and address registers
- 16-bit status register
- Data format
- Integer 8, 16 or 32-bit
- BCD packet
- Memory interface: AHB Master
- Independent data and address buses
- 4 GB-address space
- 32-bit address bus
- 32-bit data bus
- OK, RETRY, SPLIT, ERROR responses served
- Only NONSEQ access used
- Bus locking for TAS instruction
- Parameterizable endianess
- Interrupt Controller
- Seven Priority Levels
- Virtually an unlimited number of interrupt sources
- Vectored or auto-vectored interrupt modes
- Arithmetic-Logic Unit
- 8, 16, 32-bit arithmetic and logic operations
- Boolean manipulations
- 16 x 16-bit multiplication (sign or unsigned)
- 32 / 16-bit division (sign or unsigned)
- Operation execution is the same for data or address registers
- Interface for On-Chip Debug solution (optional)
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Block Diagram
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