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Serial Flash Controller Core

The SPI-MEM-CTRL core offers the interconnection between a host and a serial flash memory using the Serial Peripheral Interface. The SPI-MEM-CTRL supports Single, Dual Input, Dual Input/Output and Quad Input/Output SPI accesses.

The core automatically identifies a variety of serial flash memories and communicates with the attached device at the maximum possible bandwidth. Register accesses are used to insert access requests and read/write data into/out SPI-MEM-CTRL core. Communication with devices other than those automatically identified, is also feasible as the core can be programmed with the memory device parameters. The SPI-MEM-CTRL can read, write or erase any part of the memory.

The core is rigorously verified. A complete verification environment that helps designers verifies the functioning and compliance of the core, and additional aids for system-level simulation are available.

Features

  •  Device Independent
  •  Automatic identification of a variety of memories
  •  Configurable memory features to allow support of more serial flash devices
  •  Efficient Bandwidth Utilization
  •  Automatic identification of maximum bandwidth access mode among:
  •  single SPI
  •  dual output SPI
  •  dual input / output SPI
  •  quad input / output SPI
  •  Flexible Access Model
  •  Registered Mapped I/O
  •  Host issues access request, reads and writes data via registers access
  •  Read access sizes from 1 byte up to memory density
  •  Read accesses starting from any address offset
  •  Write access sizes from 4 bytes up to memory density
  •  Write accesses starting from any address offset that is multiple of 4 Erasure of: any sector (4KB); any block (64KB); whole chip
  •  Ease of Integration
  •  Auto-detection of a wide set of serial flash devices to minimize programming overhead
  •  Auto detection of the fastest way to read or program the memory, to maximize bandwidth and minimize programming overhead
  •  Deep Power-down Mode support to minimize power consumption
  •  Optional APB interface
  •  Design Quality
  •  Robust verification with integrated testbench environment.
  •  Scan-ready design

Block Diagram