FPGA Based Prototyping, the 'Why', 'What' and 'How' – A Real Viable Option (Part 2)
The key benefits of FPGA based prototyping are – low cost, high performance and easy deployment. In addition to these benefits, ability to interface with real-time devices allows the designer to observe the SoC prototype's behavior in the context of a real system. Low system cost makes it affordable to create multiple pre-silicon hardware platforms for software development. FPGA based prototyping offers significantly high operating performance, typically in the range of 10 MHz to 80 MHz, enabling verification of designs that are subjective in nature, such as a video frame. Higher performance also makes it practical to develop software: drivers, OS boot-up and application software – which is not possible using other verification techniques. Small footprint makes it easily deployable and portable to field for demo and testing.
SoC design typically includes a number of IPs (3rd party or legacy), custom logic, processors, memory and various bus interfaces. The design net-list (could be a mix of RTL and EDIF) cannot be mapped directly to the FPGAs due to the lack of 1 to 1 correspondence between SoC design elements and FPGA resources, such as: gated clocks, DesignWare components (optimized design components from Synopsys library), memory and any other encrypted block. Some manual changes to the RTL are often required before synthesis.
Most often, the entire SoC design is too large to fit into a single FPGA, requiring the design to be partitioned into multiple blocks corresponding to each FPGA on the prototyping board. Typically when building a prototyping system, the FPGA device selected is one with the highest logic gate count and the largest number of I/O pins. This is because you want to map largest possible design block into each FPGA, thereby reducing the total FPGA count, while simultaneously reducing the number of interconnects between FPGAs, which often explodes after partitioning, necessitating the implementation of mechanisms such as 'time division multiplexing' where multiple design signals between FPGAs are mapped to single I/O pins.
The prototyping systems do have cerProdigyn disadvantages: the design debug is not as intuitive as a in a simulator, although the debug tools have been significantly improving (including the ability debug multiple FPGAs, see VM – Verification Module, provided by www.s2cinc.com). The process of mapping and verifying the design into the board is not completely automated and needs user intervention. The overall benefits of FPGA based prototyping significantly outweigh these minor limitations. Without a doubt, the FPGA based prototyping is here to stay and a major blessing in addressing the verification challenge of complex designs.
Figure 2: Concurrent flow: Hardware verification, System integration and Software development
In a nut shell FPGA based prototypes not only serve as a pre-silicon hardware platform for software development but can be used to verify standalone IPs, run designs at real speeds, apply real-world stimuli and allow system integration. Lower cost and deploy ability makes it further economically feasible to distribute multiple systems to both hardware and software engineers. Most importantly it allows concurrent development of hardware verification, system integration and software development as shown in figure 2.
The benefits of FPGA based prototyping are compelling and have been successfully implemented by major SoC developers. The obvious question that arises is, "as a designer, should I develop my own prototyping system or buy it from a prototyping vendor". This is a very important question and answered in the blog, "Build versus Buy: FPGA based prototyping system".