FPGA Based Prototyping, the 'Why', 'What' and 'How' – Part 1

2011.11.09 | Ashok Kulkarni | AE Director, North America

Before I delve into the details of FPGA based prototyping we need to answer the question, "Why Prototype". All designs, whether they are SoC or ASIC or ASSP (hereafter SoC is also assumed to mean ASIC and ASSP), need to be verified (functional and timing) to ensure that the implemented model matches the desired behavior of the design, prior to silicon availability. Further, most SoCs are differentiated by the software content. So the availability of a pre-silicon hardware platform for software development early on, is crucial. The modern day SoC designs continue to increase in gate density, cost and complexity. Getting the silicon right the first time is an absolute necessity – failing which the cost can run into several million $$ to re-spin silicon, and a lost market opportunity can be devastating to the business. To address the verification challenge and the need of pre-silicon hardware platform a number of techniques have been proposed – this discussion addresses only the functional verification. 

Broadly you can classify them into either software based technique - using RTL simulator and hardware-assisted techniques - hardware acceleration emulation and FPGA based prototyping.

In a simulation based approach, the design under test (DUT) and the test-bench (TB) are run within a RTL simulator. This method has a number of advantages such as: low cost, ease of set-up and use, complete visibility into any portion of the simulated design. You have full controllability and observability and have the ability to apply break points and pause to observe the design behavior, as you would in a software debugger. There are many disadvantage of this approach:

  • Low Performance (typically in the range of 20-30 Hz even when run on a high end workstation) which makes it impossible to exhaustively verify all scenarios of test suites and thus it is well suited for initial block level verification only.
  • Lacks the inability to interface the design with real-time interfaces and understand its behavior in the context of a real system..
  • Not practical to develop any software on these designs.

This is where the hard-ware assisted verification comes into play. Hardware acceleration is a methodology wherein the DUT is mapped to hardware (often an array of FPGAs or custom processors) and the TB resides in the software simulator. While the performance gain over simulator is in the range of 10x to 100x, it is limited by the DUT to TB activity ratio, which can be increased to a certain degree, by implementing a transaction based TB. Further, in hardware acceleration, the DUT is verified in isolation and not within the context of a system. The high cost of hardware accelerator, its size and performance makes it impractical to create multiple systems necessary for software development.

Figure 1: SoC/ASIC Product Development Phase

Emulation, on the other hand, can be faster (more than 1000x over simulator) and offers superior debug capabilities but the size makes it non-portable. Further, the high cost of emulators makes it economically impractical to create multiple systems, which are needed for both hardware and software developers.

FPGA based prototyping addresses most of the limitations discussed above. Is FPGA prototyping a new methodology? No not really. My first prototyping project was in 1994. It was based on Xilinx XC4000 series and included 6 XC4040 FPGAs on a single board. Just to tickle my curiosity, the largest Virtex 6 FPGA device today is over 120 times denser than XC4085XL, the largest device in its family! So this begs the question what makes prototyping a real viable option? This is explored in the next blog, "Part2: FPGA Based Prototyping – A Real Viable Option".