What I think about Xilinx Virtex-7 2000T & Vivado Design Kit
In 2012, S2C successively released Single, Dual and Quad Xilinx Virtex-7 2000T FPGA-based SoC/ASIC prototyping systems. Given that the latest technology employed by Virtex-7 (V7) FPGA is new both to the industry and to S2C’s customers, many customers have called upon us to inquire about the new FPGA features and their software support. For the purpose of answering these questions, this blog provides a brief overview of the Xilinx V7-2000T FPGA, which currently boasts the largest gate capacity in the industry , and the brand-new Vivado software design kit that supports the FPGA.
About the Xilinx Virtex-7 2000T
The Virtex-7 2000T device is made from four silicon dies assembled into one package and referred to as “3D IC” by Xilinx. However, from user’s perspective, you conceive it as one extra-large FPGA similar to any previous generation FPGAs. The design implementation steps are also almost identical to those from previous generation FPGA devices.
With four 28nm silicon die in a single package, one would be curious to know how many logic cells, RAM, I/O and other resources does the Virtex-7 2000T FPGA have. The table below provides a simple comparison over S2C’s prototyping systems with largest Xilinx FPGA device from previous generation - Virtex-6 760, and the largest available Altera FPGA today, Stratix-4 820. The table also provides the same available resource information in S2C’s Dual V7 Prodigy Logic Module which uses 2 Virtex-7 2000T FPGAs and Quad V7 Prodigy Logic Module which uses 4 Virtex-7 2000T FPGAs.
Note: Xilinx Logic Cell is based on 6-input Look-up-Table (LUT) and Altera uses 4-input LUT.
As indicated by the table above, the Virtex-7 2000T FPGA is about 2.5 times larger than previous generation FPGAs when compared in terms of the most fundamental FPGA element, logic cells. For most applications, you can actually pack more than 2.5 times the design logic that could fit into previous generation FPGA into one Virtex-7 2000T FPGA, since there are abundant routing resource available compared to what you would have when partitioning a design into 3 FPGAs.
If the purpose of using Virtex-7 2000T FPGA is for prototyping, your next question might be exactly how many ASIC gates can I pack into one such device? There is always a discrepancy when converting the number of ‘Logic Cell’ elements into equivalent ASIC gates; many marketing numbers use 1 logic cell = 10 AISC gates, so they claim 20 million ASIC gates per single Virtex-7 2000T. Others use 1 logic cell = 6 AISC gates, or 12 million ASIC gates per single Virtex-7 2000T. I would say that the real answer to the Logic Cell to equivalent ASIC gate conversion ratio is design dependent, but you should use the latter number (1 to 6) for initial design mapping estimation, especially since some logic cell resources may be wasted due to routing limitations. Furthermore, if you try to pack the FPGA too full, the P&R may take a long time to process and significantly affect the design performance.
Even with the conservative estimation, i.e. lower equivalent ASIC conversion rate, an S2C Quad V7 Prodigy Logic Module with four Virtex-7 2000T devices can prototype a SoC with 48 Million ASIC gates, which should meet about 95% of today’s SoC/ASIC design capacity needs. For smaller SoC/ASIC designs, S2C offers the Dual and Single V7 Prodigy Logic Modules, which can comfortably fit 24 and 12 Million ASIC gates respectively.
It is imperative that an FPGA device with an extra-large capacity requires a design kit with adequate resources to support it. On that note, let’s take a moment to review the Vivado design kit.
About Vivado Software
With regard to Xilinx design kits, the first thing that probably pops into one’s mind is ISE software, which was released 15 years ago when the scale of design faced by designers was relatively small and the main cause of delay was attributed to logic cell placement, one-dimensional timing and routing. However, with the increasing complexity of designs, interconnections and design congestion have become the main cause of delay in large-scale data operations. According to Xilinx, despite constant upgrading, ISE could no longer provide the capabilities required by very complex FPGA such as the V7-2000T while still meeting today’s user design flows, which are often system-centric and IP-based.
Therefore, the new Vivado design kit includes a highly integrated design environment and next-generation tools ranging from system level to IC level, which are all developed on the basis of a shared extensible data model and universal debugging environment. In addition, it extensively supports various applicable industry standards, such as AMBA AXI4 interconnection specifications, IP-XACT IP encapsulated metadata, Tool Command Language (Tcl) and Synopsys Design Constraints (SDC).
The Vivado design kit also supports ESL design flow for rapid synthesis and verification of C language algorithm IP, systematic integration of reusable standard algorithm, and RTL IP encapsulating technology and various system building modules. Having adopted a hierarchical device editor and floorplanner, the Vivado tool offers a significant faster compile flow, producing improved predictability and better results. In addition, its incremental processing can rapidly process ECO sections without impacting upon performance.
Specifically for SoC/ASIC prototyping applications, I have listed three of the top key advantages of Vivado software below:
1. Support for SDC constraint files. Vivado uses the Synopsys Design Compiler constraint format instead of ISE’s original UCF file format. This can be convenient for ASIC prototyping since users usually specify timing constraints in the SDC file and thus have to modify only the SDC file suitable for FPGA implementation. Vivado SDC files allow the users to specify constraints all the way from design synthesis to placement and routing. This provides a significant advantage over ISE workflow, where users were required to specify separate constraint files for various FPGA implementation steps.
2. Multi-dimensional analysis placement engine. This feature is necessary to minimize the three design dimensions (timing, congestion and routing length), thereby significantly reducing the time taken for placement and routing for stacked silicon die such as the V7-2000T device. Below I have provided an example showing the time consumption for placement and routing of a 1.2 million-level logic cell design using the old ISE and the new Vivado design suite.
3. Reinforced ECO function. Vivado has excellent ECO function, so users do not need go through initial design steps if small design changes are needed at the later stages. With the Vivado Device Editor, users can move instances or wires, connect a register to the main output for debugging via an oscilloscope and even modify the parameters of MMCM (Clock Module). This feature ensures several things: reProdigyn the original design performance after ECO, significantly reduce the number of design iterations, and save debugging time.
In summary, Xilinx has put in a great amount of effort into the new Virtex-7 2000T FPGA and into the Vivado Software that supports the FPGA. Based on my own Virtex-7 2000T usage experiences in the past 6 months and also on numerous feedback from S2C’s customers, I feel Xilinx has done a pretty good job this time around (compared to what was available at the time when Virtex-6 760 FPGA was launched). I hope this blog provides you with a glimpse of new capabilities and the confidence to implement your next ASIC/SoC prototyping project using the new Virtex-7 2000T devices.