S2C Limited.
S2C Limited.

S2C Webinar-Debugging Techniques for FPGA Prototyping

S2C Webinar-Debugging Techniques for FPGA Prototyping Oct 09, 2021

Webinar: Debugging Techniques for FPGA Prototyping


Already familiar with FPGA debugging? How would it apply to FPGA prototyping, especially over multiple FPGAs? Find out what #S2C has to offer in this 8-minute video.

  • Time: Octotber 09, 2021 (CST)

  • Location: Online



Details about Webinar:


  • Basic debugging techniques such as VIO IP & Source/Probes Editor are available from FPGA vendors

  • Internal/Embedded Logic Analyzer available in Vivado/Quartus

    -Only support single FPGA debug and consumes FPGA resources

  • S2C offers additional FPGA prototyping debugging approaches to increase your high productivity

    -Basic IO, UARTs and Virtual IOs -ProtoBridge to offer high bandwidth AXI connectivity over PCIe

    -NT Bus to offer mid bandwidth connectivity AXI over Ethernet

    -MDM Pro to provide concurrent data sampling over multiple FPGAs

    -Over 90+ daughter cards to support in-system testing and protocol connectivity

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What type of chip are you designing
What is the capacity of the ASIC gate included in the design?
5 million-20 million
20 million-50 million
50 million-100 million
100 million-1 billion
More than 1 billion
Which FPGA do you prefer to use?
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Xilinx KU115
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Intel S10-10M
Intel S10-2800
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Segmentation tool
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