In IC (integrated circuit) design, hardware emulation imitates the behavior of one or more pieces of hardware (typically a system under design) with another piece of hardware, typically a special-purpose emulation system. The emulation model usually bases on a hardware description language (e.g., Verilog) source code, which is compiled into the format used by the emulation system. The goal is typically debugging, and functional verification of the system being designed.
Modern Emulators tend to focus on providing highly automated and versatile verification – support for multiple programming languages, high design under test (“DUT”) model capacity (1 billion gate equivalents and more), high levels of bring-up automation (a few weeks) that minimizes manual intervention, support for multiple verification modes such as transaction-based acceleration (“TBA”), in-circuit emulation (“ICE”), and Quick Emulator (“QEMU”) mode, targeting multiple usage scenarios for system-level functional verification of chip and IP designs and embedded software verification. It requires the longest set-up time (a few weeks) and is the most expensive (around millions of dollars).
Generally speaking, hardware emulation is a hardware-accelerated simulation. It provides high capacity and full visibility for trading off performance and cost. Hardware emulation has a substantially higher execution speed than simulation ( to 1MHz) and offers excellent insight into the RTL. However, it requires the longest set-up time (a few weeks) and is the most expensive (around millions of dollars). A well-funded design team may have an emulator or two to catch 90% of the hardware bugs.
Supports multiple programming languages
Can handle both system-level designs (in C, C++, or SystemC) and RTL designs (in Verilog, System Verilog, or VHDL).
Higher design visibility and hence higher debug capability
Strong signal debugging capabilities, support static probe, dynamic probe, full visibility of the signal.
Parallel verification of many designs possible
