S2C Limited.
S2C Limited.


Calculator Nov 17, 2022

About the Prototyping Calculator:

This calculator generates graphs showing the performance crossover point for emulation vs. FPGA-based prototyping.

- Enter values for Bring up Time, Clock Speed, Unit Test Time, and Cost per Gate.

- Enter Number of Runs and click Calculate.

The graph plots the Number of Runs against Time. Time is calculated from the Number of Runs multiplied by the Unit Test Time. A given Unit Test Time is specified for Emulation, which then generates the Unit Test Time for prototyping, using the ratio of Clock Speeds.

The plot also accounts for Bring up Time, which adds an offset to each curve. The Number of Runs determines how far out to calculate the curves.

A second curve for prototyping is generated showing the effect of running prototypes in parallel (replicates). This curve is generated using the ratio of Cost per Gate.

The table shows Elapsed Time in hours as well as days (both 8-hour days, and running 24/7.

Request for Quote
What type of chip are you designing
What is the capacity of the ASIC gate included in the design?
5 million-20 million
20 million-50 million
50 million-100 million
100 million-1 billion
More than 1 billion
Which FPGA do you prefer to use?
Xilinx VU440
Xilinx KU115
Xilinx VU19P
Xilinx VU13P
Xilinx VU9P
Intel S10-10M
Intel S10-2800
Not sure, need professional advice
What kind of FPGA configuration do you need?
Single FPGA
Four FPGAs
Eight FPGAs
Not sure, need professional advice
What kind of peripheral interface do you need?
How many prototype verification platforms do you need?
Do you need the following tools?
Segmentation tool
Multiple FPGA debugging tools
Co-modeling tool (allows large amounts of data to interact between FPGA and PC host)
When do you need to use our products?
0-6 months
6-12 months
More than 12 months
Not sure
Any additional comments?