S2C Limited.
S2C Limited.

Formal Verification

What is formal verification?

Formal verification uses mathematical techniques to show if a design complies with one or more formal criteria or attributes. This method is used in the design of computer hardware, particularly integrated circuits (IC) and software systems.

The most fundamental need for the chip is the design function's accurate implementation. Hence formal verification is required to ensure the accuracy of the chip design. A successful verification effort may significantly reduce the semiconductor design cycle. Formal verification is distinct from simulation, which is crucial for implementing integrated circuits.

Why formal verification is important?

As design sizes and simulation times have increased, verification teams have explored techniques to reduce the number of vectors required for system operation to acceptable coverage. Formal verification may be completed quickly because it is not necessary to assess every potential state to demonstrate that a given logic fulfills a given set of properties under all circumstances. However, the kind of reasoning used and how it is applied significantly impact how well it performs.

Furthermore, formal verification is a systematic process that utilizes mathematical reasoning to assess whether the intended purpose (RTL) has been achieved. Since formal verification can thoroughly check all potential input values, it can solve simulation-related problems.

When to use formal verification

  • If RTL designs might suffer severe (and expensive) error escapes (Pentium FDIV) because of insufficient corner case coverage during simulation testing.

  • A new RTL module was designed, and the designer wished to simulate it for testing purposes without having to spend weeks building a testbench.

  • Parts of the RTL were tweaked to pass synthesis, and weeks of simulation were spent to ensure that no real changes were made to its functionality.

  • The fact that fresh faults keep cropping up in the later phases of verifying the design shows that the previous stage's random simulations did not offer sufficient coverage.

  • Modified the design's control register specifications, which required extensive simulation to verify that the RTL modifications worked as intended.

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Methodology For Soc / ASIC Application Demands

Request for Quote
What type of chip are you designing
What is the capacity of the ASIC gate included in the design?
5 million-20 million
20 million-50 million
50 million-100 million
100 million-1 billion
More than 1 billion
Which FPGA do you prefer to use?
Xilinx VU440
Xilinx KU115
Xilinx VU19P
Xilinx VU13P
Xilinx VU9P
Intel S10-10M
Intel S10-2800
Not sure, need professional advice
What kind of FPGA configuration do you need?
Single FPGA
Four FPGAs
Eight FPGAs
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What kind of peripheral interface do you need?
How many prototype verification platforms do you need?
Do you need the following tools?
Segmentation tool
Multiple FPGA debugging tools
Co-modeling tool (allows large amounts of data to interact between FPGA and PC host)
When do you need to use our products?
0-6 months
6-12 months
More than 12 months
Not sure
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