Functional simulation is the process of verifying the functional behavior of a design by simulating it in software. It does not consider the timing delays of the internal logic or interconnects and is not helpful in software development.
The purpose of simulation is to verify the individual IPs or the individual blocks of the IC.
Quick to set up
High visibility in the design
Bugs are identified early in the design
All corner cases of the designs are verified
Very slow speed
Complex designs are not easily simulated
Verification of the entire IC is difficult
All possible scenarios and states are not covered
Verification of software is not possible
Timing-related issues are not identified