Prodigy™ Logic Matrix is a high-density FPGA prototyping platform architected from the ground up to meet today's needs for both hyperscale design verification and operation performance. Optimized for space and connectivity, Logic Matrix is designed for multi-system expansion to support billions of ASIC gate capacity. This platform is ideal for addressing the ever-increasing complexity and performance requirements in large-scale SoC designs for applications such as 5G, data center, AI/ML, and autonomous driving.
Industry-leading density and capacity-up to 3.136 billion ASIC gates in single standard server rack
Hierarchical connectivity to support flexible topology and hyperscale design verification at prototyping performance
Highly modular design to simplify deployment, maintenance, and expansion in standard server racks
Multi-usages: early software development, full system prototyping, high performance regression
|Logic Matrix LX2 Configuration Table|
|Estimated ASIC Gates (M)||98||196||294||392|
|FPGAs||2 * XCVU19P||4 * XCVU19P||6 * XCVU19P||8 * XCVU19P|
|System Logic Cell (M)||17.8||35.7||53.6||71.5|
|FPGA Memory (Mb)||331.8||663.6||995.4||1327.2|
|Prodigy Connectors (144 IOs)||18||36||54||72|
|MCIO Connectors (4 GTY + 8 IOs)||40||80||120||160|
|Logic Matrix LX1 Configuration Table|
|Estimated ASIC Gates (M)||60||120||180||240|
|FPGAs||2 * XCVU440||4 * XCVU440||6 * XCVU440||8 * XCVU440|
|System Logic Cell (M)||11.1||22.1||33.2||44.3|
|FPGA Memory (Mb)||177.2||354.4||531.6||708.8|
|Prodigy Connectors (144 IOs)||16||32||48||64|
|PGT Connectors (8 GTH + 8 IOs)||2||4||6||8|
|MSAS Connectors (4 GTH + 8 IOs)||20||40||60||80|
Logic Matrix address high-performance prototyping by providing a flexible connectivity architecture with 3 levels of hierarchy: ShortBridge with interconnection modules between neighboring FPGAs; SysLink to connect FPGAs over high bandwidth cables, and TransLink for longer distance links between FPGA SerDes over MCIO cables.
More usable gates per FPGA means fewer FPGAs, fewer FPGA interconnects, and higher performance for the same prototyped design. With an estimated gate capacity of 392 million gates per LX2, a fully populated standard server rack with 8 LX2's enables an estimated prototyping capacity of over 3 billion ASIC gates.
Hyperscale designs now range into the billions of ASIC gates. Although these complex designs are demanding, LX2 combines the largest FPGA available from Xilinx with an architecture designed for interconnect optimization. Constructed to ensure high reliability and robust operation, the LX2 addresses enterprise-class considerations including real-time system monitors, efficient cooling, and redundant hot-pluggable power supplies.