We all know that complexities in design and shrinking time-to-market windows are driving up design and verification costs. Simulation and emulation, although useful, are slow and for the later also costly. Furthermore, both simulation and emulation can hit a wall when it comes to identifying critical corner case bugs. A hardware platform such a FPGA prototyping is more cost-effective and much faster with the ability to test system designs at speed to provide an accurate assessment of design behavior. However, compiling complex designs to multiple FPGAs can still be time-consuming and debugging designs with multiple FPGAs can be difficult.
When an SoC design must be partitioned into multiple FPGAs to build an FPGA prototype, design partitioning adds complexity to the FPGA prototyping effort. Design partitioning adds to the first FPGA prototype bring-up effort, it adds to the time needed to update the prototype with design fixes, and it adds the complexity of maintaining good prototype visibility for debugging. Design partitioning has been one of the guiding implementation considerations for multi-FPGA prototyping since - well, since early emulators were implemented using FPGAs.
To simplify FPGA interconnect while addressing bandwidth and flexibility, S2C also introduced hierarchical connectivity: ShortBridge, SysLink, and TransLink, each with different granularity to manage local, Logic Matrix-to-Logic Matrix, and rack-to-rack interconnect. ShortBridge provides high throughput connectivity between neighboring FPGAs, SysLink connects FPGAs over high bandwidth cables, and TransLink supports longer distance links between FPGAs with SerDes over copper or optical cables.
S2C’s newest generation of FPGA prototyping products offers the latest FPGAs from Xilinx and Intel - and they are available in single, dual, and quad-FPGA variants. The Prodigy Player Pro is a tool that works with the FPGA-based prototyping platforms from S2C. It integrates three development processes into one - it configures the prototyping, runs remote system management, and provides set-ups for multi-FPGA debugging. Such an integrated solution alleviates the pain of tackling the complex FPGA flow and plays a significant role in the FPGA prototyping methodology.