S2C Limited.
S2C Limited.


What is Hardware Emulation?

In IC (integrated circuit) design, hardware emulation imitates the behavior of one or more pieces of hardware (typically a system under design) with another piece of hardware, typically a special-purpose emulation system. The emulation model usually bases on a hardware description language (e.g., Verilog) source code, which is compiled into the format used by the emulation system. The goal is typically debugging, and functional verification of the system being designed.

Why do IC designers need Hardware Emulation?

Modern Emulators tend to focus on providing highly automated and versatile verification – support for multiple programming languages, high design under test (“DUT”) model capacity (1 billion gate equivalents and more), high levels of bring-up automation (a few weeks) that minimizes manual intervention, support for multiple verification modes such as transaction-based acceleration (“TBA”), in-circuit emulation (“ICE”), and Quick Emulator (“QEMU”) mode, targeting multiple usage scenarios for system-level functional verification of chip and IP designs and embedded software verification. It requires the longest set-up time (a few weeks) and is the most expensive (around millions of dollars).

Generally speaking, hardware emulation is a hardware-accelerated simulation. It provides high capacity and full visibility for trading off performance and cost. Hardware emulation has a substantially higher execution speed than simulation ( to 1MHz) and offers excellent insight into the RTL. However, it requires the longest set-up time (a few weeks) and is the most expensive (around millions of dollars). A well-funded design team may have an emulator or two to catch 90% of the hardware bugs.

What are the benefits of hardware emulation?

  • Supports multiple programming languages

    Can handle both system-level designs (in C, C++, or SystemC) and RTL designs (in Verilog, System Verilog, or VHDL).

  • Higher design visibility and hence higher debug capability

    Strong signal debugging capabilities, support static probe, dynamic probe, full visibility of the signal.

  • Parallel verification of many designs possible

S2C Related Complete Prototyping Solutions

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What type of chip are you designing
What is the capacity of the ASIC gate included in the design?
5 million-20 million
20 million-50 million
50 million-100 million
100 million-1 billion
More than 1 billion
Which FPGA do you prefer to use?
Xilinx VU440
Xilinx KU115
Xilinx VU19P
Xilinx VU13P
Xilinx VU9P
Intel S10-10M
Intel S10-2800
Not sure, need professional advice
What kind of FPGA configuration do you need?
Single FPGA
Four FPGAs
Eight FPGAs
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What kind of peripheral interface do you need?
How many prototype verification platforms do you need?
Do you need the following tools?
Segmentation tool
Multiple FPGA debugging tools
Co-modeling tool (allows large amounts of data to interact between FPGA and PC host)
When do you need to use our products?
0-6 months
6-12 months
More than 12 months
Not sure
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