S2C Limited.
S2C Limited.

CAST Deciphers Security System Design Challenges with New AES Encryption IP

CAST Deciphers Security System Design Challenges with New AES Encryption IP Dec 03, 2008

Woodcliff Lake, NJ, December 3, 2008—Silicon Intellectual Property(IP)provider CAST, Inc. today announced a new family of AES IP cores that make it easier for designers to include fast hardware encryption in security-sensitive electronic systems.

AES — the Advanced Encryption Standard — is the cryptographic algorithm mandated by US government agencies and used extensively to protect data around the world. The new CAST IP covers a range of AES requirements by offering a programmable, multi-purpose encrypt/decrypt core and a leaner pre-configured core with versions optimized for specific applications.

The CAST AES cores are available now, for either ASICs (HDL source code) or FPGAs (netlists). An introductory discount of 20% is available through the end of the year (December 31, 2008).

"With five years experience working with AES IPs and helping eighty-some customers use encryption cores successfully, we've never seen AES products as efficient, flexible, and easy to integrate as this latest generation," said Hal Barbour, president of CAST, Inc., "The special 20% discount makes these cores a real bargain for design teams that can order by December 31."

About AES Encryption

The Advanced Encryption Standard (AES) is an implementation of the Rijndael block cipher encryption algorithm. In 2001 the US National Institute of Standards and Technology (NIST) approved it as Federal Information Processing Standard Publication 197 (FIPS 197).

The algorithm accepts a block of input data, processes it using a supplied encryption key, and outputs a block of encrypted data. (Decryption works in the reverse, using the same key.) Longer key lengths make the encryption more secure, and various cipher modes can modify the operation of the basic algorithm. AES can be executed in software, but hardware-based AES is generally required for real-time data encryption or decryption.

Learn more about AES including an explanation of its cipher modes and hardware design issues in a White Papers at www.cast-inc.com/encryption.

CAST's New AES IP Cores

The new AES core family was developed by long-time CAST partner Alma Technologies S.A., in Greece. Two basic products cover a broad range of user requirements for silicon area, transmission bit rate, power consumption, and degree of encryption protection:

  • The AES-P programmable core offers multi-use flexibility in a single module, with built-in support for all five common block cipher modes (ECB, CBC, CFB, OFB, and CTR) and real-time switching among them as needed.

  • The AES-C codec core offers a leaner implementation, requiring half the chip area with better performance but supporting just one block cipher mode (selected prior to synthesis).

  • An efficient design allows each core to handle both encryption and decryption as needed, simplifying system integration. Each can also be real-time switched to use 128-, 192-, or 256-bit long encryption keys, trading off quicker processing with greater protection.

Two architectural options are available for each core: one uses a 32-bit data path so it requires less chip area and needs 44 clock cycles for AES processing (with a 128-bit key); the other uses a 128-bit data path so it is a little larger but only needs 11 clock cycles.

CAST believes the cores yield implementation results and data transmission rates (throughput) as good or better than competing products. Multiple ASIC and FPGA implementation statistics are readily available on the CAST website.

Strong encryption technology like these new AES IP cores is governed internationally by strict export regulations. Immediate export of the cores to many countries is already approved, and CAST's encryption sales asSoCiates can answer questions and give advice concerning others. See the CAST website for more information, or call +1 (201) 391-8300.

In China, all the cores are available through S2C ( www.s2cinc.com), please contact sales@s2cinc.com for more information.


Lawrence Liang, Sales Director of China Region, S2C Inc. +86 21 6887 9287, lawrencel@s2cinc.com

Lam Cheng En, Marketing Consultant, S2C Inc., +86 21 6887 9287, lamce@s2cinc.com

Back to list Back to list
Related S2C Complete Prototyping Solutions
Stratix 10 Series
S2C's Stratix 10 Prodigy Logic Systems offers easy and cost-effective path to higher density FPGA. The Stratix10 Prodigy Logic Systems are available in the following FPGAs: Stratix 10GX2800 and GX10M.
Connector Connectivity
Prodigy Interconnection Module Type CConnects 144 GPIO and 4 SerDes between two Prodigy I/O connectors.The spacing between two connectors is 75mm.Available TypesReference ClockP-PM-IMCFixed 100MHzP-PM...
Prodigy ProtoBridge
FPGA-based prototypes closely resemble final silicon chips in speed and accuracy, providing significant value in full-chip validation and early software development. Realizing these benefits has histo...
What's New at S2C
Request for Quote
What type of chip are you designing
What is the capacity of the ASIC gate included in the design?
5 million-20 million
20 million-50 million
50 million-100 million
100 million-1 billion
More than 1 billion
Which FPGA do you prefer to use?
Xilinx VU440
Xilinx KU115
Xilinx VU19P
Xilinx VU13P
Xilinx VU9P
Intel S10-10M
Intel S10-2800
Not sure, need professional advice
What kind of FPGA configuration do you need?
Single FPGA
Four FPGAs
Eight FPGAs
Not sure, need professional advice
What kind of peripheral interface do you need?
How many prototype verification platforms do you need?
Do you need the following tools?
Segmentation tool
Multiple FPGA debugging tools
Co-modeling tool (allows large amounts of data to interact between FPGA and PC host)
When do you need to use our products?
0-6 months
6-12 months
More than 12 months
Not sure
Any additional comments?