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White paper: A Multi-FPGA Based Platform for emulating a 100M-transistor-scale Processor with High-speed Peripherals

This published paper describes how Institute of Computing Technology (ICT), Chinese Academy of Science used S2C Dual Virtex-5 TAI Logic Modules to prototype a 100 million transistor-scale processor at 25MHz to boot unmodified operating system for carrying out a variety of architectural explorations. The paper identified several key challenges when prototyping a complex design onto multiple FPGA devices and how the ICT research engineers were able to solve these challenges including FPGA partitioning, pin limitations, emulating high-speed IO and debugging the design on S2C's TAI Logic Module.

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What type of chip are you designing

What is the capacity of the ASIC gate included in the design?

5 million-20 million

20 million-50 million

50 million-100 million

100 million-1 billion

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Xilinx VU440

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Segmentation tool

Multiple FPGA debugging tools

Co-modeling tool (allows large amounts of data to interact between FPGA and PC host)

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