S2C Limited.
S2C Limited.
Verification Flow

Funictional Verification

What is functional verification?

In EDA (electronic design automation), functional verification verifies that the logic design conforms to specification. Functional verification does not confirm the correctness of the design specification and assumes that the design specification is correct. It is one of the most challenging steps of the IC design cycle and is the main reason for IC re-spin.

Why is functional verification necessary?

In the 2020 Wilson Research Group Functional Verification Study, figure 1 shows various categories of design flaws contributing to IC/ASIC re-spins, where the percentage of “logic or functional flaws” remains the leading cause of bugs.

asic type of flaws contributing to respin

Figure 1: Type of ASIC Flows Contributing to Re-spin

Functional verification can be attacked by many methods, but none of them are perfect. Each can be helpful in certain circumstances.

  • Logic simulation

  • Emulation

  • FPGA-based Prototyping

  • Formal verification

Purpose of the functional verification

  • Functional correctness of individual IPs

  • Internal module communication

  • External module communication

  • End to end functional paths

  • Pad connectivity

  • Clock and reset circuits

  • Power up and down sequence

  • Complete integration of all IPs

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Memory Modules
DDR3 Memory Module, DDR3 Memory Module Type B, 8GB DDR4 Non-ECC,16GB DDR4 ECC
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What type of chip are you designing
What is the capacity of the ASIC gate included in the design?
5 million-20 million
20 million-50 million
50 million-100 million
100 million-1 billion
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Which FPGA do you prefer to use?
Xilinx VU440
Xilinx KU115
Xilinx VU19P
Xilinx VU13P
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Intel S10-10M
Intel S10-2800
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Segmentation tool
Multiple FPGA debugging tools
Co-modeling tool (allows large amounts of data to interact between FPGA and PC host)
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0-6 months
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