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White Paper: Advanced SoC Debug with Multi-FPGA Prototyping | SemiWiki

White Paper: Advanced SoC Debug with Multi-FPGA Prototyping | SemiWiki Apr 21, 2022

by Daniel Nenni on 04-19-2022 at 10:00 am

Categories: EDA;Prototyping, S2C EDA

S2C EDA recently released a whitepaper written by a good friend of mine Steve Walters. Steve and I have worked together many times throughout our careers and I consider him to be one of my trusted few, especially in regards to prototyping and emulation. Steve is also my co author on the book "Prototypical II The Practice of FPGA-Based Prototyping for SoC Design". Prototypical II and this 10 page white paper are available on the S2C EDA website HERE.


As SoC designs advance in complexity and performance, and software becomes more sophisticated and SoC-dependent, SoC designers face a relentless push to "shift left" the co-development of the SoC silicon and software to improve time-to-market.  Consequently, SoC verification has evolved to include multi-FPGA prototyping, and higher prototype performance, to support longer runs of the SoC design prototype, running more of its software, prior to silicon – in an effort to avoid the skyrocketing costs associated with silicon respins.  While FPGA prototyping for SoC design verification by its nature remains a "blunt instrument", FPGA prototyping is still the only available pre-silicon verification option, beyond hardware emulation, for achieving longer periods of SoC design operation capable of running software, and, in some cases, "plugging" the SoC design prototype directly into real target-system hardware.  Not surprisingly, commercial FPGA prototype suppliers are using the latest FPGA technology to implement FPGA prototyping, offering multi-FPGA prototyping platforms, and advancing FPGA prototyping debug tool capabilities, to meet customer demands for more effective SoC verification.

Ideally, SoC design debug tools for FPGA prototyping would enable software simulation-like verification and debug at silicon speeds – providing visibility of all internal SoC design nodes, not impede prototype performance, provide unlimited debug trace-data storage, and be quickly reconfigurable for revisions to the SoC design and/or the debug setup.  In reality, today's SoC design debug tools for FPGA prototyping falls short of the ideal, and multi-FPGA prototyping adds to the challenge of achieving ideal SoC design debug tool capabilities.  As a result, today's FPGA prototyping for SoC design debug offers tradeoffs among the ideal debug tool capabilities, and it is left to the SoC design verification team to configure an "optimal" verification strategy for each SoC design project – with consideration for future scaling-up and improved verification capabilities.

This white paper reviews some of the multi-FPGA prototyping challenges for SoC design verification and debug, and, reviews one example of a commercially available multi-FPGA prototyping debug capability offered by S2C Inc., a leading supplier of FPGA prototyping solutions for SoC design verification and debug (s2ceda.com).

Summary and Conclusions

S2C's MDM Pro hardware, together with S2C's Prodigy FPGA prototyping platforms, and S2C's Player Pro software, implements a rich set of debug features that provides SoC designers with the flexibility to optimize the FPGA prototype debug tools for a given FPGA prototyping project.  MDM Pro combines off-FPGA hardware for “deep” trace-data storage and complex hardware trigger logic, in combination with probe multiplexing IP in the FPGA to access a large number of debug probes over a few FPGA high-speed GTY connections to minimize the consumption of FPGA I/O, and the ability to setup more probe connections than need to be viewed at the same time so that more probes may be viewed when needed without recompiling the FPGA or degrading the debug performance.  Player Pro software for debug compliments the debug hardware with a powerful user interface for managing the debug setup, configuring advanced trace-data trigger conditions, initiating debug runs of the FPGA prototype, and viewing the debug trace-data from multiple FPGAs in a single viewing window.

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