Jun 24, 2025 by Daniel Nenni on 06-24-2025 at 6:00 am
Categories: EDA, Emulation, FPGA, Prototyping, S2C EDA
Qualifying an AI-class RISC-V SoC demands proving that wide vectors, deep caches, and high-speed I/O operate flawlessly long before tape-out. At the recent Andes RISC-V Conference, Andes Technology and S2C showcased this by successfully booting a lightweight large language model (LLM) inference on a single S2C Prodigy™ S8-100 logic system powered by AMD's Versal™ Premium VP1902 FPGA.
Capacity and Timing — Solved in One Device
Prototyping an SoC traditionally requires partitioning the design across multiple FPGAs, complicating timing closure and increasing development risks. S2C's S8-100 Logic System, with roughly 100 million usable gates on a single FPGA, removes these hurdles. The dual-core AX45MPV cluster from Andes— featuring 64-bit in-order cores and a powerful 512-bit vector processing unit — together with an AE350 subsystem occupies less than 40% of the FPGA capacity. This generous margin allows designers to add custom instructions, additional accelerators, debug logic or secret sauce without a second board. More importantly, the entire design can now reside within a single FPGA in S8-100, eliminating the need for time-consuming partitioning and avoiding cross-chip latency that would otherwise throttle performance. Freed from the architectural compromises of multi-FPGA systems, the design can be operated at a speed enough to run large-scale software — enabling faster iterations, more realistic validation, and a dramatically simpler prototyping flow.
Robust Memory Bandwidth Without Board Spins
LLM inference workloads require stable, high-throughput memory subsystems to continuously feed vector engines. By leveraging S2C’s pre-validated DDR4 memory module and a plug-and-play auxiliary I/O card that handles JTAG and UART, the LLM demo is easily deployed. This modular approach allowed the hardware platform to be operational within days of receiving RTL code, accelerating design iterations and debugging cycles.
Modularity That Adapts to Changing Needs
The S8-100 excels at flexibility. Developers can rapidly pivot across use cases — whether AI inference, video processing, networking, or safety-critical industrial control — by swapping daughtercards to match the desired interfaces. S2C provides a vast library of over 90 daughter cards covering interfaces from MIPI-DPHY, HDMI and 10/100/1000/100G/400G Ethernet to fieldbus protocols. When a single FPGA isn't enough, multi-FPGA partitioning is available.
Real Hardware Data Cuts Time-to-Market
Running Linux bring-up, driver stacks, and model benchmarks on cycle-accurate hardware transforms estimations into actionable insights. Teams using this approach typically save six to twelve months on critical paths with quantified risks rather than assumptions, which improves confidence in first-silicon success and ready-to-integrate software.
With Andes–S2C collaboration, developers now have better platform to innovate, explore ideas, and evaluate system architectures. By providing the capacity and flexibility to explore, the S8-100 enables teams to quickly build and iterate on proof-of-concept designs at more reasonable system performance—paving the way for faster, more confident RISC-V and AI development.
Visit s2cinc.com to request an evaluation. Our experts will provide detailed feedback in days—not months—helping you streamline your prototyping journey.
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