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What Are The Main Reasons For The Failure Of Soc Design Tape-Out?

What Are The Main Reasons For The Failure Of Soc Design Tape-Out? Sep 22, 2022

Can you believe that experienced people’s words have already become a golden rule in the industry. Moore, an insider, has done it, "The number of transistors that can be accommodated on an IC will double about every 18 months, and the performance will also double."

Since then, the development trend of chips cannot be said to be the same, but to be exactly the same. The size is getting smaller and the scale is getting bigger. Hundreds of millions of transistors are placed in a chip the size of a fingernail, and the manufacturing process has reached the nanoscale invisible to the naked eye, which can only be done by extreme ultraviolet lithography. The exponential increase in integration and complexity has directly caused the development of the entire chip to become a particularly expensive thing. It is as difficult as the pilgrimage to the West for Buddhist Sutra to successfully design an SoC.



What are the main reasons for tape-out failure?


Tape-out is the only way to the success of chip design, but the failure is also commonplace. There are many reasons for tape-out failure, with logical or functional errors accounting for almost 50% of all factors. And design errors account for 50% to 70% of the entire functional defects, becoming the number one enemy of engineers. Therefore, verification is the key to the success or failure of SoC design. After all, this society does not have tape-out insurance to buy.

But SoC verification is extremely complex, accounting for about 70% of the entire development time. To shorten the development cycle, system software development verification and pre-cast verification must be parallelized, which makes prototyping far more advantageous than others.



How important is a mature prototyping solution?


In the past, some engineers would choose to make their own prototyping boards, but the complex design segmentation, timing optimization, board debugging and other issues require engineers to have very rich experience. Coupled with the explosion of large-scale designs, the entire development cycle became extremely stressful.

Engineers are in desperate need of a proven, complete prototyping solution for large-scale SoC designs. At present, only a few leading prototyping system solution providers can meet the need.

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